1. Field of the Invention
The invention pertains generally to ceramic chip carriers and, more particularly, to ceramic chip carriers which include lead frames or edge clips, or pins.
2. Description of the Related Art
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a ceramic, e.g., alumina, substrate. Typically, such a semiconductor chip package, conventionally termed a ceramic chip carrier, is intended for mounting on a printed circuit card or printed circuit board. If surface mounting is to be used, then, conventionally, a ceramic chip carrier will include a lead frame which is mechanically and electrically connected to electrical contact pads formed around the periphery of the chip-bearing, circuitized surface of the ceramic substrate.
Ceramic chip carriers of the type referred to above include both single-layer and multi-layer ceramic substrates. In the former case, the chip carrier is fabricated by initially circuitizing an upper surface of the single ceramic layer using conventional thick film metal screening techniques. The metal employed is, for example, an alloy of silver (Ag) and palladium (Pd), which has a melting temperature of 1145.degree. C. and an electrical resistivity of 20.times.10.sup.-8 ohm-meters (.OMEGA.-m). The resulting circuit lines typically have thicknesses and widths of, for example, 0.5 mils and 3 mils, respectively. After circuitization, the resulting ceramic layer is fired in air at a temperature of, for example, 850.degree.-950.degree. C. which is readily withstood by the Ag-Pd alloy. A semiconductor chip or chips is then mounted on the circuitized surface using conventional wire bonding techniques.
In the fabrication of a multi-layer ceramic substrate, each ceramic layer is usually circuitized using conventional thick film screening techniques, and these circuitized ceramic layers are then cured and laminated together at firing temperatures of, for example, 1900.degree. C. To withstand these high temperatures, the circuitry on each of the circuitized layers typically consists of a refractory metal such as molybdenum (Mo) or tungsten (W), which have melting temperatures equal to or greater than 2625.degree. C. and corresponding electrical resistivities equal to or greater than 5.2.times.10.sup.-8 .OMEGA.-m. As before, a chip or chips is conventionally mounted on the multi-layer ceramic substrate using conventional wire bonding techniques.
Regardless of whether the ceramic chip carrier includes a single-layer substrate or a multi-layer substrate, a lead frame has conventionally been mechanically and electrically connected to contact pads on such a ceramic chip carrier using conventional brazing techniques. The braze materials employed have included, for example, alloys of indium (In) - copper (Cu) - silver (Ag) and Cu-Ag, and the brazing temperatures have been as high as 750.degree. C.
Significantly, the brazed joints between the lead frames and ceramic substrates of the ceramic chip carriers, described above, exhibit what is considered to be acceptable thermal fatigue resistance. That is, these joints readily withstand a standard thermal fatigue test during which they are subjected to sinusoidal temperature cycling between 0.degree. C. and 100.degree. C., at a frequency of three cycles per hour, for at least 2000 cycles without any significant increase in electrical resistance, i.e., any increase in electrical resistance, if it occurs, is less than 200 milliohms.
Currently, there is a need to reduce the width of the circuit lines on the circuitized surfaces of ceramic chip carriers to a value equal to or less than about 1 mil, while simultaneously reducing the thickness of the circuit lines and contact pads to a value equal to or less than about 0.3 mils. This is readily accomplished by a conventional thin film/subtractive etch process in which a metal layer is blanket deposited onto a ceramic substrate by conventional sputtering or evaporation techniques and then patterned via chemical etching to define circuitry on the ceramic surface. To avoid increasing the electrical resistances of the circuit lines, etchable metals having electrical resistivities equal to or less than about 6.times.10.sup.-8 .OMEGA.-m, such as copper (which has an electrical resistivity of 1.7.times.10.sup.-8 .OMEGA.-m), are employed.
There is now also a need to achieve a relatively high density of chip connections on ceramic substrates, which is not achievable using the conventional wire bonding technique. However, this is now readily accomplished using the so-called flip chip technique in which one or more chips are mounted face-down on solderable metal pads on a ceramic substrate, using solder balls. In this regard, a patterned layer of chromium on the copper circuitry is needed to serve as a solder dam, i.e., to control the solder volume of the solder ball connections.
Attempts to braze lead frames to ceramic chip carriers employing copper circuitry in combination with chromium solder dams, at the brazing temperatures associated with braze materials such as In-Cu-Ag and Cu-Ag alloys, have resulted in the chromium solder dams diffusing into the copper circuitry, making flip chip joining impossible. Consequently, brazing lead frames to such ceramic chip carriers, using these braze materials, is inappropriate.
Thus, those engaged in developing ceramic chip carriers have sought, thus far without success, a ceramic chip carrier which includes:
(1) thin film circuitry of, for example, copper in combination with a solder dam of, for example, chromium on a ceramic substrate, PA1 (2) one or more semiconductor chips mounted in a flip-chip configuration on the circuitized ceramic substrate using solder balls, PA1 (3) a lead frame connected to contact pads on the circuitized surface of the ceramic substrate, in which the mechanical/electrical connections are formed at temperatures below the temperature at which the solder dam diffuses into the circuitry, and PA1 (4) mechanical/electrical connections which are capable of withstanding the standard thermal fatigue test.